RAMP Project TALX:
Corrected RFS due date: May 29, 2020.
Solutions for RAMP due no later than 12 PM EDT on Friday, May 29, 2020
The United States Navy and Air Force, in support of the Office of the Secretary of Defense (OSD), is developing integrated circuit (IC) hardware and workflow prototypes that promote the use of assurance principles, feature protections, and correlation. The purpose of this prototype is to facilitate the rapid development of IC hardware for further evaluation and technology enablement of DoD, while simultaneously generating workflow prototypes using commercial best practices for DoD defense industrial base (DIB).
The RAMP project intends to address and replace the obsolete practices utilized by the United States Government in support of State-of-the Art (SOTA) custom IC and System On a Chip (SoC) design, especially those associated with physical or “back-end” design. These current, outdated processes have resulted in the effectiveness of the Department of Defense (DoD) and the traditional Defense Industrial Base (DIB) being significantly superseded by commercial industries and other non-DoD markets in the design and fabrication of SOTA ICs and SOCs.
As such, the Navy and Air Force desires to leverage commercial capabilities to develop a RAMP prototype methodology to demonstrate secure enhanced design utilizing commercial fabrication processes for DoD’s programs. The emphasis on physical design refers to the post Registered Transfer Language (RTL) portion of design that includes automated place and route, timing closure, and verification of the physical design. Physical design is particularly challenging because the design methods used are tightly coupled with specific fabrication processes and facilities and because physical design has become more and more complex as semiconductor processes have become more advanced.
The primary objective of the RAMP prototype project is to leverage the expertise of commercial industry to develop and demonstrate a novel capability for design of SOTA (defined as ≤ 22nm node Si CMOS) ICs and SoCs microcircuits that can be designed and verified in the most advanced semiconductor processes. In addition, a RAMP prototype will achieve lower power consumption, improved performance, reduced physical size, and improved reliability for application in DoD systems. It is important to note that this prototype supports, but does not directly address Packaging or Radiation Hard circuit design. These areas are addressed by other DoD programs.
Achieving the objective will require novel and innovative methods including unique and secure design tools and critical circuit modules required to design advanced custom ICs and SoCs. Secure IC and SoC design resources will also be developed to support successful demonstration of the RAMP prototype. This objective also requires a complex IP licensing and support model, and close fab relationships