S²MARTS Project No. 21-07
This opportunity has been awarded to Qualcomm Technologies and Intel Technologies
The Department of Defense (DoD) currently has no on-shore access to foundry technology capable of meeting the long-term leading edge (<7nm Digital Complementary Metal-Oxide Semiconductor (CMOS) node) microelectronics fabrication needs for DoD specific designs or commercial-off-the-shelf (COTS) components. Most of the leading United States (U.S.) fabless semiconductor companies manufacture their components off-shore. There is currently no commercially viable leading edge pure-play foundry option on-shore that will keep the U.S. industry on the leading edge of microelectronic integrated circuit fabrication needs.
Most U.S. microelectronics design companies are fabless, meaning that these companies design and sell integrated circuits through outsourcing their fabrication to a specialized manufacturer called a semiconductor foundry. These foundries are typically, but not exclusively, located in Asia, primarily in Taiwan and South Korea. Fabless companies benefit from lower capital costs while concentrating their research and development resources on the end market. There is currently no commercially viable option that can provide a U.S. located leading-edge foundry that can fabricate the assured leading-edge custom integrated circuits and Commercial off the Shelf (COTS) products required for critical DoD systems. The purpose of the RAMP-C program is to incentivize such an option.
Office of Secretary Defense Research & Engineering (OSD R&E) has programs that are critical and complementary to the RAMP-C program: Rapid Assured Microelectronics Prototypes using Advanced Commercial Capabilities (RAMP) and digital State of the Art Heterogeneous Integrated Packaging (SHIP). Jointly SHIP, RAMP, and RAMP-C will address the entire Microelectronics design/manufacturing cycle. RAMP addresses the critical process of physical design (also called back-end design) that transforms a high-level programming form register-transfer level (RTL) of a design into the complex, technology specific polygon form of a design that is required as input for the wafer fabrication process. RAMP facilitates DoD use of advanced commercial design capabilities in a quantifiably assured environment. SHIP will develop the capability to use advanced commercial heterogeneous integration and advanced packaging technology to package and test the integrated circuits designed in RAMP and fabricated in the leading-edge commercial facility developed in RAMP-C. All three programs will assure access to advanced capabilities in facilities located in the U.S. Confidentiality and integrity of commercial and DoD designs will be assured using Quantifiable Assurance methods across all three programs.
Collectively, the three programs, SHIP, RAMP, and RAMP-C display the following critical characteristics:
- Ensures DoD access through leveraging U.S. located, commercially developed technology that is made viable through extensive use by high-volume commercial companies.
- Measurably assures the confidentiality and integrity of DoD leading edge integrated circuits through use of Quantifiable Assurance methods integrated across the microelectronic design/manufacturing enterprise.
- Facilitates use of advanced integrated circuit technology by the Defense Industrial Base (DIB) by leveraging learning from best-in-class commercial partners.
