Microelectronics Commons Quantum Technology

Call for Projects

Call for Projects Quantum Awards

Northeast Microelectronics Coalition (NEMC)

• • Community‐driven Hybrid Integrated Quantum‐Photonic Integrated circuits (CHIQPI) ($9.6M) 
    • Project focused on the creation of a community-accessible, manufacture-grade quantum-classical hybrid integration platform with the potential to significantly reduce the size, weight, power and cost of quantum systems for use in Department of Defense applications.

Northeast Regional Defense Technology Hub (NORDTECH)

• • Improved Materials for Superconducting Qubits with Scalable Fabrication ($8.9M) 
    • NY CREATES and partners in academia, industry, and government will co-develop technologies necessary to demonstrate scalable quantum error correction, using new materials, innovative quantum circuits and qubit control schemes.
  • Quantum Ultra-broadband Photonic Integrated Circuits and Systems (QUPICS) ($8.5M) 
    • The QUPICS team, led by the American Institute for Manufacturing Integrated Photonics (AIM Photonics) and Cornell University, will develop a novel 300mm foundry fabrication platform for quantum technologies which will span the ultraviolet to the infrared.
  • Heterogeneous Quantum Networking ($3.9M) 
    • The Rochester Institute of Technology, AFRL, and partners plan to realize a heterogeneous quantum network (HQN) that connects ion-based qubits with superconducting and photonic-based qubits using high speed photonics chips.

Call for Projects Amendment

The Microelectronics Commons Call for Projects has been amended.

A summary of amendments are as follows:

D1 – Added Submission Directions
D2 – Added EDA Tools and IP and Core Access Report // Letters of Support// References//Added Does not count towards 20-page limit
D3(c)- Added EDA Tools / Letters of Support/Heilmeier Responses/References
D4 – Added 15) Identify technology area, topic number(s), and project proposal number XX of 15 (e.g Project Proposal 1 of 15)
D5- Title change to “ Contents of Price Response”
D5 – Removed “severable” from instructions table (Payable Milestone Schedule)

You can find the complete amended Call for Projects under Key Documents.

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Project Background

In 2023, the Department of Defense (DoD) established the Microelectronics Commons – a network of eight regional Hubs to evolve laboratory prototypes to fabrication prototypes and to strengthen the semiconductor workforce. Annually, Hubs will compete for project awards. These annual project awards may include infrastructure (physical, digital, and human) required to accomplish the proposed prototypes. This Call for Projects (CFP) describes the desired capabilities for which project proposals are being sought.

Microelectronics Commons Hub facilities include laboratory prototype capabilities, which typically includes ≤100 mm and ≤200 mm tooling for compound semiconductor and silicon based technologies, respectively. Hubs can also generate and mature prototypes for Cores to scale up for subsequent potential selection by the National Semiconductor Technology Center (NSTC) and/or industrial microelectronics companies, such as fabless or Integrated Device Manufacturers (IDMs), for commercialization. The role of the regional Hubs is to connect researchers and designers to prototyping capabilities targeted to strengths in the Hub’s technical topic areas.

Microelectronics Commons Cores are fabs/foundries, manufacturing facilities where semiconductor devices are manufactured, that have scalable capacity for prototyping beyond what the regional Hubs can provide (fab prototyping). They are available for use by innovators that run the gamut from university and small business up to large industrial concerns. Cores typically have 300 mm capabilities for silicon-based technologies (other sizes are technology appropriate) and are facilities that can demonstrate prototypes with the volume and characteristics required to ensure reduced risk for manufacturing. Cores serve a dual function: First, they serve to further complement and advance the work of the regional Hubs; i.e., they are integral to the Hubs themselves. For example, they provide capabilities at ≥200 mm wafer fab for silicon complimentary metal-oxide-semiconductor- (CMOS-) compatible technologies and ≥100 mm wafer fab for compound semiconductors. Second, they serve to engage with commercial fabs and better align regional Hubs to commercial processes to facilitate transition of technologies.

Current State and Desired End-State

Innovative prototypes to include microelectronics materials, processes, devices, and architectural designs will be supported. Activities executed within Microelectronics Commons shall primarily fall under Budget Activity (BA) 3, although activities that fall under Budget Activities 2 and 4 will also be supported if they are in support of the lab-to-fab prototype. (e.g., BA 2 activities may be needed to support iterative development, and BA 4 activities may be needed to support the transition of a project to DoD demonstrators.)

For further discussion on research, development, testing, and evaluation (RDT&E) budget activities, see the DoD Financial Management Regulation, DoD 7000.14-R, Volume 2B, Chapter 5. (VOLUME_2B (defense.gov).

For further discussion on Manufacturing Readiness Levels (MRLs), see the Manufacturing Readiness Level (MRL) Deskbook, Version 2.0. https://www.dodmrl.com/MRL_Deskbook_V2.pdf

Microelectronics Commons will support prototype projects across six technical areas that are critical to the DoD. Those areas are: Secure Edge/Internet of Things Computing, 5G/6G Technology, Artificial Intelligence Hardware, Quantum Technology, Electromagnetic Warfare, and Commercial Leap Ahead. Specifically, prototype projects that achieve the desired capabilities as described in the Desired Capabilities document (Attachments c-h) are being sought. The current state, desired end-state, and success criteria for those prototype projects are included in the Desired Capabilities document.

The end-state goal is microelectronics hardware-focused prototyping and lab-to-fab transition of semiconductor technologies. For lab-to-fab prototyping, the fab prototype must at least match if not exceed lab prototype technical specifications, and there must be a path to manufacturability in a Core (i.e., a foundry or fab). Projects that have been demonstrated in a lab and are ready for prototyping in a fab will have higher priority than lab prototyping projects.

View the full Call for Projects (CFP) under Key Documents on the right side of the page.

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Quantum Technology Projects

Quantum Technology Topic 1: Quantum-Photonic Integration

Quantum Technology Topic 2: Superconducting Quantum Error Correction Qubit

Quantum Technology Topic 3: Quantum Trapped Ion/Neutral Atom Integration

Quantum Technology Topic 4: Solid State-Based Quantum Device Accelerator

Quantum Technology Topic 5: Distributing and Transducing Entanglement

To view the full Quantum Technology projects, please refer to the technical guide found under Key Documents on the right side of the page.

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